1. Field of the Invention
The present invention relates to semiconductor memory devices and particular to configurations of a memory cell select circuit and those of a redundant circuit thereof.
2. Description of the Background Art
In recent years, as microprocessors (MPUs) are improved in operating speed, there has been used synchronous DRAM (SDRAM) operating in synchronization with a clock signal to achieve rapid access e.g. of a dynamic random access memory (DRAW used as a main memory device.
Internal operation of such an SDRAM and the like is divided into row- and column-related operations for control.
The SDRAM and the like also employ a bank configuration, the memory cell array divided into banks each capable of independent operation, to achieve further rapid operation. More specifically, for each bank, the operation is controlled independently with respect to the row- and column-related operations.
Typically, a word line is hierarchically configured by main and subordinate word lines to reduce the load to be driven by a drive circuit to provide for rapid operation in the operation of selecting a row of the memory cell array or a word line in the row-related operation.
In semiconductor memory devices such as an SDRAM and the like having a conventional multibank configuration, however, the hierarchical configuration described above disadvantageously results in an increased number of the elements required for selecting a subordinate word line.
Furthermore, in recent years a memory circuit and a logic circuit are integrated on a single chip to provide e.g. chips on which a DRAM and a logic circuit are mounted mixedly for the purpose of achieving multifunction, improving data processing speed and the like. For this type of chips, the data bus width for communicating data between a storage device such as a DRAM and a logic circuit that are integrated on a single chip, i.e., the number of bits of data communicated at one time, tends to be increased to provide rapid process.
Furthermore, an input/output line (an I/O line pair) transmitting data read from a memory cell to an interface circuit is often configured hierarchically in view of enhancement of operating speed and the like. To transmit data from a memory cell via the hierarchical I/O line pair, a gate circuit is provided therebetween for selectively connecting a bit line pair connected to the memory cell selected in a read operation and the I/O line pair communicating the data. For multibank, memory cell arrays, such a gate circuit also tends to be increased in the number of elements used therefor. Particularly, inputting and outputting data on a bus with such a large bus width as described above requires an increased number of independently operable I/O line pairs. This also increases the number of the gate circuits described above and hence the number of elements configuring the gate circuits.
An object of the present invention is to provide a semiconductor memory device with a memory cell array capable of efficient select operation with reduced number of the elements of a circuit for selecting a memory cell in the memory cell array.
Another object of the present invention is to provide a semiconductor memory device with a memory cell array configuration capable of reducing the number of elements used for a data communication path for reading data.
The present invention is a semiconductor memory device including a memory cell array, a plurality of main word lines, a plurality of subordinate word lines, a main row select circuit, a subordinate row select circuit, a block select circuit, a plurality of block select lines, and a plurality of drive circuits.
The memory cell array has a plurality of memory cells arranged in rows and columns. The memory cell array is divided into a plurality of memory cell blocks in rows and columns.
The plurality of main word lines are arranged in the direction of the rows of the memory cell array, shared by a plurality of memory cell blocks arranged in the direction of the rows of the memory cell array. The plurality of subordinate word lines correspond to respective rows of memory cells in the memory cell blocks such that a first plurality of the plurality of subordinate word lines are provided for each main word line. The main row select circuit is provided for the memory cell array and selectively activates a main word line in response to an address signal. The subordinate row select circuit is provided for the memory cell array, indicating which subordinate word line is activated out of the first plurality of subordinate word lines in response to an address signal. The block select circuit responds to an address signal to indicate which memory cell block has been selected. The plurality of block select lines are activated in response to an indication of block selection from the block select circuit.
The plurality of drive circuits are each provided for a subordinate word line, driving a potential of the associated subordinate word line in response to an indication from the subordinate row select circuit and activation of the associated block select line and activation of the associated main word line.
Each drive circuit includes a first switch circuit transmitting a potential level from a main word line in response to activation of a block select line, and a hold circuit activated in response to an output level of the switch circuit and an indication from the subordinate row select circuit to hold selection-indicating information for an associated subordinate word line and drive a potential of the associated subordinate word line.
The main row select circuit and the block select circuit reset a level of a main word line and a level of a block select line after the selection-indicating information is completely transmitted to the hold circuit.
In another aspect of the present invention, a semiconductor memory device includes a memory cell array, a row select circuit, a block select circuit, a plurality of redundant memory cell blocks, and a redundancy determination circuit.
The memory cell array has a plurality of memory cells arranged in rows and columns. The memory cell array is divided into a plurality of memory cell blocks in rows and columns.
The row select circuit is provided for the memory cell array, selecting a row of memory cells in response to an address signal. The block select circuit responds to an address signal to indicate which memory cell block has been selected.
The plurality of redundant memory cell blocks are provided independently of the memory cell blocks. The redundancy determination circuit previously stores a memory cell block and address at which a defective memory cell is located and the redundancy determination circuit selects a redundant memory cell within a redundant memory cell block when a memory cell designated according to an address signal corresponds to the defective memory cell.
In accordance with the present invention, the memory cell array can be advantageously divided and thus operated to reduce electricity consumption. Furthermore, the divided memory cell blocks arranged in rows and columns can enhance the degree of freedom in circuit configuration when multibit data are communicated concurrently.
Still advantageously, in accordance with the present invention a redundant memory cell in the redundant memory cell blocks provided independently of the memory cell array can be substituted for a defective memory cell to enhance the efficiency with which the redundant memory cell is substituted for the defective memory cell.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.